Cambridge AS & A Level Computer Science
4.1Central Processing Unit (CPU) architecture
Central Processing Unit (CPU) architecture in Cambridge AS & A Level Computer Science: what the syllabus expects you to know, the learning objectives and how to practise.
Subtopic81 practice questions4 lessons
Learning objectives
What the syllabus expects you to be able to do.
- 4.1.1Describe the Von Neumann model, the stored-program concept and the roles of registers, the ALU, control unit, system clock and immediate access store.
- 4.1.2Describe how data moves between components over the address, data and control buses.
- 4.1.3Explain how processor type, cores, bus width, clock speed and cache affect performance, and how ports connect peripherals (USB, HDMI, VGA).
- 4.1.4Describe the fetch-execute cycle in register transfer notation.
- 4.1.5Explain the purpose, causes and handling of interrupts and the use of an interrupt service routine.
Lessons
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Buses and ports
40 min
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CPU architecture: Von Neumann, Harvard and registers
45 min
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Processor performance
40 min
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The fetch-execute cycle and interrupts
50 min
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Sample question
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